45 research outputs found

    Parallel Prefix and Reduction Algorithms Using Coterie Structures

    No full text
    : The efficient computation of region parameters in image understanding by a SIMD array requires that those regions be processed simultaneously. The difficulty lies in orchestrating non-uniform data-dependent communication using only a single thread of control. We introduce a novel new technique we call coterie structures for the simultaneous parallel processing of connected components on reconfigurable broadcast meshes. Our technique differs fundamentally from those previously used for this class of networks in that each region is processed using only those PEs to which that region is mapped. Simultaneous and efficient region processing is thereby effected without remapping. The primary theoretical result is that techniques similar to those used in PRAM graph contraction algorithms can be used to create an optimal randomized reduction algorithm and near optimal deterministic algorithms for reduction and parallel prefix in all regions simultaneously. The primary practical result is a r..

    Message-Passing Algorithms for a SIMD Torus with Coteries

    No full text
    This paper describes the results of an investigation into routing algorithms to be used when programming the CAAPP (Content Addressable Array Parallel Processor) [19], a SIMD mesh-connected array processor enhanced with the coterie network, a mechanism similar to reconfigurable buses. We will show that the coterie network gives the CAAPP a capability far beyond solely meshconnected processors; in fact, the performance of routing on many classes of permutations is more comparable to the Connection Machine which has a dedicated hypercube routing network. Most of the current routing algorithms for meshconnected array processors (with N PEs in an n \Theta
    corecore